The first set of Papers is by Himanshu Thapiyal who is foremost leader in implementing the Vedic Math sutras to the use of Information Technology.Himanshu Thapliyal received his B.Tech in Computer Engineering in 2004 from G.B. Pant University of Agril. & Technology, Pantnagar, India.Currently,he is doing MS by research under Dr. M.B Srinivas(Head),Centre for VLSI & Embedded System Technologies, International Institute of Information Technology, Hyderabad, India. He has participated in various International and National conferences and workshops. He has published nearly 40 research papers in reviewed International Conferences and Journals. He was awarded 1 lakh rupees by the State Government of Uttaranchal for his research on Vedic Mathematics, and for the participation in conferences in USA & UK.He has also worked with Dr. Hamid R.Arabnia, University of Georgia, U.S.A.Currently, he is also working with Dr. Mark Zwolinski,University of Soutampton, U.K. His website can be found at These Papers have been presented at various conferences around the world organised by NASA, Various Security Companies, IBM, Intel etc. Links to specific pages on these organization’s websites can be requested for further study. 1) VLSI Implementation of RSA Encryption System Using Ancient Indian Vedic Mathematics by Himanshu Thapliyal This paper proposes the hardware implementation of RSA encryption/decryption algorithm using the algorithms of Ancient Indian Vedic Mathematics that have been modified to improve performance. The recently proposed hierarchical overlay multiplier architecture is used in the RSA circuitry for multiplication operation. The most significant aspect of the paper is the development of a division architecture based on Straight Division algorithm of Ancient Indian Vedic Mathematics and embedding it in RSA encryption/decryption circuitry for improved efficiency.The coding is done in Verilog HDL and the FPGA synthesis is done using Xilinx Spartan library. The results show that RSA circuitry implemented using Vedic division and multiplication is efficient in terms of area/speed compared to its implementation using conventional multiplication and division architectures. www.vedicmathsindia.org/Vedic Math IT/1.VLSI Implementation of RSA encryption system using Vedic Math.pdf
2) Time-Area- Power Efficient Multiplier and Square Architecture Based On Ancient Indian Vedic Mathematics by Himanshu Thapliyal and Hamid R.Arabnia
In this paper new multiplier and square architecture is proposed based on algorithm ancient Indian Vedic Mathematics, for low power and high speed applications. It is base on generating all partial products and their sums in one step. The design implementation is described in both at gate level and high level RTL code (behavioural level) using Verilog Hardware Description Language. The design code is tested using Veriwell Simulator. The code is synthesized in Synopys FPGA Express using: Xilinx,Family: Spartan Svq300, Speed Grade: -6. The present paper relates to the field of math coprocessors in computers and more specifically to improvement in speed and power over multiplication and square algorithm implemented in coprocessors. In FPGA implementation it has been found that the proposed Vedic multiplier and square are faster than array multiplier and Booth multiplier. 3) A High Speed and Efficient Method of Elliptic Curve Encryption Using Ancient Indian Vedic Mathematics by Himanshu Thapliyal and M.B.Srinivas Abstract—This paper presents for point doubling using square algorithms of Ancient Indian Vedic Mathematics. In order to calefficient hardware circuitry culate the square of a number, “Duplex” D property of binary numbers is proposed. A technique for computation of fourth power of a number is also being proposed. A considerable improvement in the point additions and doubling has been observed when implemented using proposed techniques for exponentiation.
The Next Paper is by Prof. Purushottam Chidgupkar and Prof.Mangesh Karad on Digital Signal Processing ( DSP). It has been published in the Global Journal of Engineering Education. Prof. Purushottam D.Chidgupkar, Ex-Commander of the Indian Navy and postgraduate from Cranfield University, UK, has been at the MIT campus since January 1998. He has made noteworthy contributions in the development of one of thebest IT infrastructure at the MIT Women Engineering College, Maharahstra Academy of Engineering and Educational Research, Pune, India. His own specialisation is in the area of digital signal processing (DSP) and has, to his credit, quite a few research projects completed under his close guidance. He has also been exploring Vedic mathematics concepts for their usability in DSP. His research thus far has given ample evidence of the better efficiency of Vedic algorithms and their implementation in computers with reduced processing times. He intends to design separate processor architecture suitable for Vedic approaches and achieve further improvements in processing time. 4) The Implementation of Vedic Algorithms in Digital Signal Processing by Purushottam D. Chidgupkar and Mangesh T. Karad Digital signal processing (DSP) is the technology that is omnipresent in almost every Engineering discipline. It is also the fastest growing technology this century and, therefore, it poses tremendous challenges to the engineering community. Faster additions and multiplications are of extreme importance in DSP for convolution, discrete Fourier transforms digital filters, etc. The core computing process is always a multiplication routine; therefore, DSP engineers are constantly looking for new algorithms and hardware to implement them. Vedic mathematics is the name given mto the ancient system of mathematics, which was rediscovered, from the Vedas between 1911 and 1918 by Sri Bharati Krishna Tirthaji. The whole of Vedic mathematics is based on 16 sutras (word formulae) and manifests a unified structure of mathematics. As such, the methods are complementary, direct and easy. The authors highlight the use of multiplication process based on Vedic algorithms and its implementations on 8085 and 8086 microprocessors, resulting in appreciable savings in processing time. The exploration of Vedic algorithms in the DSP domain may prove to be extremely advantageous. Engineering institutions now seek to incorporate research-based studies in Vedic mathematics for its applications in various engineering processes. Further research prospects may include the design and development of a Vedic DSP chip using VLSI technology. The Next set of Papers is by Talented Young Engineering and Computer Students. Shripad Kulkarni is pursuing the Master of Engineering in Process Instrumentation. He has correlated one process in Digital Signal Processing and compared it with the Vertically and Crosswise process of Vedic maths. Also done analysis tried to show how number of multiplication and additions reduce time and process. 5) Discrete Fourier Transform (DFT) by using Vedic Mathematics by Shripad Kulkarni. Though there are many algorithms for the same task only VAN-NEUMAN architectural implementation of classical method is found to be used in present day digital computers. The Vedic mathematical methods suggested by Shankaracharya Sri. Bharti Krishna Tirthaji through his book offer efficient alternatives. The present seminar analyses and compares the implementation of DFT algorithm by existing and by Vedic mathematical technique . It is suggested that architectural level changes in the entire computation system to accommodate the Vedic mathematical method shall increase the overall efficiency of DFT procedure. 6) Kunal Singh and Vinesh Raicha are pursuing Masters of Science in Computer Science and their partner Rohit Jog who is also an MSc in Computer Science is currently working with Symantec.They show some Vedic Math Algorithm Applications in their Paper and show other useful application of Vedic Math in the field of IT with their diagrams. All Papers are Copyrighted to their respective authors.Please Add to comments for your feedback.